1. Field of the Invention
The embodiments of the invention relate to memory and pipeline management. Specifically, the embodiments of the invention relate to maintaining memory coherence in an out of order processor pipeline.
2. Background
Processors in a computer utilize a pipeline and multiple execution units to process instructions out of order to improve system performance. Processing instructions out of order allows a processor to execute more instructions in a given time period because the processor is able to process multiple instructions simultaneously and to execute instructions that are ready to be processed immediately while other instructions are stalled. Instructions may be stalled because they require data to be retrieved from a memory device, storage device or input device.
Compilers may be programmed to facilitate out of order processing. Compilers may group or order instructions out of original program order based on static information known at compile time. One technique a compiler may use is to advance a load instruction from its original program order position. Load instructions often entail delay in processing because they may require a retrieval of data from memory. Retrieving data from memory is significantly slower than the execution of an instruction that does not require a memory access. Advancing the placement of loads increases the chances that the load will complete its memory access before the loaded data is needed by subsequent instructions allowing for their immediate execution as they occur in program order.
Hardware structures in a pipeline may perform similar optimization procedures based upon dynamic information known to the processor at run time. The pipeline architecture may detect an upcoming load and advance its processing or pre-fetch the needed data in memory.